Transistors are key components of modem integrated circuits. To satisfy the requirements of increasingly faster speed, the drive currents of transistors need to be increasingly greater. Since the drive currents of transistors are proportional to gate widths of the transistors, transistors with greater widths are preferred.
The increase in gate widths, however, conflicts with the requirements of reducing sizes of semiconductor devices. Fin field effect transistors (FinFET) are thus formed. FIG. 1 illustrates a perspective view of a conventional FinFET. Fin 4 is formed as a vertical silicon fin extending above substrate 2, and is used to form source and drain regions 6 and a channel region therebetween (not shown). A vertical gate 8 intersects the channel region of fin 4. While not shown in FIG. 1, a gate dielectric separates the channel region from vertical gate 8. FIG. 1 also illustrates oxide layer 18, and insulating sidewall spacers 12 and 14 formed on source and drain regions 6 and vertical gate 8, respectively. The ends of fin 4 receive source and drain doping implants that make these portions of fin 4 conductive. The channel region of fin 4 is also doped.
In the FinFET as shown in FIG. 1, the channel width is close to W+2H, wherein W is the width of fin 4, and H is the height of fin 4. The drive currents of FinFETs are thus increased without incurring the penalty of chip area. However, in conventional schemes for forming FinFETs, all FinFETs on a given chip have the same fin height, limiting the capability for customizing the performance of FinFETs. A solution is thus needed.